description the l6219ds motor driver is designed to drive both windings of a bipolar stepper motor or bidirectionally control two dc motors. both bridges are capable of sustaining 45 v and include internal pulse-width modulation (pwm) control of the output current to 750 ma. the outputs have been optimized for a low output saturation voltage drop (less than 1.8 v total source plus sink at 500 ma). for pwm current control, the maximum output current is determined by user selection of a reference voltage and sensing resistor. two logic-level inputs select output current limits of 0, 33, 67, or 100% of the maximum level. a phase input to each bridge determines load current direction. the bridges include both ground clamp and flyback diodes for protection against inductive transients. internally generated delays prevent crossover currents when switching current direction. special power-up sequencing is not required. thermal protection circuitry disables the outputs if the chip temperature exceeds safe operating limits. the l6219ds is supplied in a 24-pin surface-mountable soic, with 4 internally-fused leads for maximum package power dissipation in the smallest possible construction. it is lead (pb) free with 100% matte tin leadframe plating. 29319.43h features and benefits ? interchangeable with sgs l6219ds ? 750 ma continuous output current ? 45 v output sustaining voltage ? internal clamp diodes ? internal pwm current control ? low output saturation voltage ? internal thermal shutdown circuitry ? similar to dual pbl3717, uc3770 dual full-bridge pwm motor driver package: 24 pin soicw (suffix lb) typical application not to scale A6219DS from p v ref dwg. ep-008b1 v bb from p 1 2 3 4 5 6 7 8 9 24 23 22 21 20 17 16 15 14 13 12 11 10 9 q 2 v cc 2 v bb 1 v ref +5 v stepper motor r s r s r c r c r t c t c c c c + pwm 1 pwm 2 q 1 820 pf 56 k 7 c t 820 pf 56 k 7 r t 19 18
dual full-bridge pwm motor driver l6219ds 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units motor supply voltage v bb 45 v logic supply voltage v cc 7.0 v logic input voltage range v in ?0.3 to v cc +0.3 v output emitter voltage v sense 1.5 v output current, peak i out(pk) 1.0 a output current, continuous i out output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do not exceed the speci ed peak current rating or a junction temperature of +150c. 750 ma operating ambient temperature t a range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing operating ambient temperature range t a (c) l6219ds-t 31 pieces per tube ?20 to 85 l6219dstr-t 1000 pieces per reel ?20 to 85 thermal characteristics characteristic symbol test conditions* value units package thermal resistance r ja 1-layer pcb with copper limited to solder pads 77 oc/w 1-layer pcb with 3.57 in. 2 of copper area 49 oc/w r jt 6 oc/w *additional thermal information available on the allegro website. 50 75 100 125 150 2.5 1.5 1.0 0.5 0 temperature in c 2.0 25 dwg. gp - 019c r = 6c/w jt r = 77c/w ja r = 49c/w ja
dual full-bridge pwm motor driver l6219ds 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ? 1998, 2003 allegro microsystems, inc. pwm current-control circuitry v ref dwg. ep-007-5 v bb comp in one shot source disable rc ? + i 0 i 1 w 10 sense out a out b channel 1 terminal numbers shown. r c r s r t c c c t 24 20 k 7 40 k 7 10 k 7 21 1 23 22 14 20 17 15 pin-out diagram 1 2 3 4 5 6 7 8 24 23 22 21 20 17 16 15 14 13 12 11 10 9 q 2 q 1 v cc pwm 2 pwm 1 2 v bb 1 ground ground ground ground 02 i 12 i phase 2 v ref 2 2 rc 1 rc v ref 1 phase 1 11 i 2b out sense 2 2 comp in 2a out 1a out 1 comp in sense 1 1b out 01 i load supply logic supply dwg. pp-005-3 19 18 phase truth table phase out a out b hh l llh
dual full-bridge pwm motor driver l6219ds 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com limits characteristic symbol test conditions min. typ. max. units output drivers (out a or out b ) motor supply range v bb 10 ? 45 v output leakage current i cex v out = v bb ? < 1.0 50 a v out = 0 ? <-1.0 -50 a output sustaining voltage v ce(sus) i out = 750 ma, l = 3.0 mh 45 ? ? v output saturation voltage v ce(sat) sink driver, i out = +500 ma ? 0.4 0.6 v sink driver, i out = +750 ma ? 1.0 1.2 v source driver, i out = -500 ma ? 1.0 1.2 v source driver, i out = -750 ma ? 1.3 1.5 v clamp diode leakage current i r v r = 45 v ? < 1.0 50 a clamp diode forward voltage v f i f = 750 ma ? 1.6 2.0 v driver supply current i bb(on) both bridges on, no load ? 20 25 ma i bb(off) both bridges off ? 5.0 10 ma control logic input voltage v in(1) all inputs 2.4 ? ? v v in(0) all inputs ? ? 0.8 v input current i in(1) v in = 2.4 v ? <1.0 20 a v in = 0.8 v ? - 3.0 -200 a reference voltage range v ref operating 1.5 ? 7.5 v current limit threshold v ref /v compin i 0 = i 1 = 0.8 v 9.5 10 10.5 ? i 0 = 2.4 v, i 1 = 0.8 v 13.5 15 16.5 ? i 0 = 0.8 v, i 1 = 2.4 v 25.5 30 34.5 ? thermal shutdown temperature t j ? 170 ? c total logic supply current i cc(on) i 0 = i 1 = 0.8 v, no load ? 40 50 ma i cc(off) i 0 = i 1 = 2.4 v, no load ? 10 14 ma fixed off-time t off r t = 56 k , c t = 820 pf ? 46 ? s (at trip point) electrical characteristics at t a = +25c, t j 150c, v bb = 45 v, v cc = 4.75 v to 5.25 v, v ref = 5.0 v (unless otherwise noted).
dual full-bridge pwm motor driver l6219ds 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com applications information pwm current control the l6219ds dual bridge is designed to drive both windings of a bipolar stepper motor. output current is sensed and controlled independently in each bridge by an external sense resistor (r s ), internal comparator, and monostable multivibrator. when the bridge is turned on, current increases in the motor winding and it is sensed by the external sense resistor until the sense voltage (v compin ) reaches the level set at the comparator?s input: i trip = v ref /10 r s the comparator then triggers the monostable which turns off the source driver of the bridge. the actual load current peak will be slightly higher than the trip point (especially for low- inductance loads) because of the internal logic and switching delays. this delay (t d ) is typically 2 s. after turn-off, the motor current decays, circulating through the ground-clamp diode and sink transistor. the source driver?s off time (and therefore the magnitude of the current decrease) is determined by the monostable?s external rc timing components, where t off = r t c t within the range of 20 k to 100 k and 100 pf to 1000 pf. the xed-off time should be short enough to keep the current chopping above the audible range (< 46 s) and long enough to properly regulate the current. because only slow-decay current control is available, short off times (< 10 s) require additional efforts to ensure proper current regulation. factors that can negatively affect the ability to properly regulate the current when using short off times include: higher motor-supply voltage, light load, and longer than necessary blank time. when the source driver is re-enabled, the winding current (the sense voltage) is again allowed to rise to the comparator?s threshold. this cycle repeats itself, maintaining the average motor winding current at the desired level. loads with high distributed capacitances may result in high turn-on current peaks. this peak (appearing across r s ) will attempt to trip the comparator, resulting in erroneous current control or high-frequency oscillations. an external r c c c time delay should be used to further delay the action of the comparator. depending on load type, many applications will not require these external components (sense connected to comp in). + C 0 dwg. wm-003-1a v phase i out t d t o i trip dwg. e p-006-1 r s bb v bridge on source off all off pwm output current wave form load current paths
dual full-bridge pwm motor driver l6219ds 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com logic control of output current two logic level inputs (i 0 and i 1 ) allow digital selection of the motor winding current at 100%, 67%, 33%, or 0% of the maximum level per the table below. the 0% output current condition turns off all drivers in the bridge and can be used as an output enable function. these logic level inputs greatly enhance the implementation of p-controlled drive formats. during half-step operations, the i 0 and i 1 allow the p to control the motor at a constant torque between all positions in an eight- step sequence. this is accomplished by digitally selecting 100% drive current when only one phase is on and 67% drive current when two phases are on. logic highs on both i 0 and i 1 turn off all drivers to allow rapid current decay when switching phases. this helps to ensure proper motor operation at high step rates. the logic control inputs can also be used to select a reduced current level (and reduced power dissipation) for ?hold? conditions and/or increased current (and available torque) for start-up conditions. general the phase input to each bridge determines the direction motor winding current ows. an internally generated dead time (approximately 2 s) prevents crossover currents that can occur when switching the phase input. all four drivers in the bridge output can be turned off between steps (i 0 = i 1 2.4 v) resulting in a fast current decay through the internal output clamp and yback diodes. the fast current decay is desirable in half-step and high-speed applications. the phase, i 0 ,and i 1 inputs oat high. varying the reference voltage (v ref ) provides continuous control of the peak load current for microstepping applications. thermal protection circuitry turns off all drivers when the junction temperature reaches 170c. it is only intended to protect the device from failures due to excessive junction temperature and should not imply that output short circuits are permitted. the output drivers are re-enabled when the junction temperature cools to 145c. the l6219ds output drivers are optimized for low output saturation voltages?less than 1.8 v total (source plus sink) at 500 ma. under normal operating conditions, when combined with the excellent thermal properties of the fused internal lead package design, this allows continuous operation of both bridges simultaneously at 500 ma. current-control truth table l 0 i 1 output current ll v ref /10 r s = i trip hl v ref /15 r s = 2/3 i trip lh v ref /30 r s = 1/3 i trip hh 0
dual full-bridge pwm motor driver l6219ds 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com current sensing to minimize current sensing inaccuracies caused by ground trace ir drops, each current-sensing resistor should have a separate return to the ground terminal of the device. for low-value sense resistors, the ir drops in the pcb can be signi cant and should be taken into account. the use of sockets should be avoided as their contact resistance can cause variations in the effective value of r s . generally, larger values of r s reduce the aforementioned effects but can result in excessive heating and power loss in the sense resistor. the selected value of r s should not cause the absolute maximum voltage rating of 1.5 v, for the sense terminal, to be exceeded. the recommended value of r s is in the range of: r s = 0.75 / i trip (max) 50% . if desired, the reference input voltage can be ltered by placing a capacitor from refin to ground. the ground return for this capacitor as well as the bottom of any resistor divider used should be independent of the high-current power-ground trace to avoid changes in refin due to ir drops. thermal considerations for reliable operation, it is recommended that the maximum junction temperature be kept below 110c to 125c. the junction temperature can be measured best by attaching a thermocouple to the power pins (6, 7, 18 and 19) of the device and measuring the pin temperature, t tab . the junction temperature can then be approximated by using the formula: t j = t tab + (2 i load v f r jt ) , where v f can be chosen from the electrical speci cation table for the given level of i load . the value for r jt is approximately 6c/w. the power dissipation can be improved 20% to 30% by adding a section of printed circuit board copper (typically 6 to 18 square centimeters) connected to the power pins of the device. the thermal performance in applications that run at high load currents, high duty cycles, or both can be improved by adding external diodes from each output to ground in parallel with the internal diodes. fast-recovery ( 200 ns) diodes should be used to minimize switching losses. load supply terminal the load supply terminal, vbb, should be decoupled with an electrolytic capacitor ( 47 f is recommended), placed as close to the device as is physically practical. to minimize the effect of system ground ir drops on the logic and reference input signals, the system ground should have a low-resistance return to the load supply voltage. fixed off-time selection with increasing values of t off , switching losses decrease, low- level load current regulation improves, emi reduces, pwm frequency decreases, and ripple current increases. the value of t off can be chosen for optimization of these parameters. for applications where audible noise is a concern, typical values of t off should be chosen in the range of 15 to 35 s. application information
dual full-bridge pwm motor driver l6219ds 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?1998-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com 1.27 b reference pad layout (reference ipc soic127p1030x265-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b 0.20 0.10 0.41 0.10 2.20 0.65 9.60 1.27 2 1 24 a 15.400.20 2.65 max 10.300.33 7.500.10 c seating plane c 0.10 24x for reference only pins 6 and 7, and 18 and 19 internally fused (reference jedec ms-013 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 0.25 gauge plane seating plane pcb layout reference view 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 package lb, 24-pin soicw
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